Synchronous logic has been, and will continue to be for the foreseeable future, the dominant design paradigm of digital systems. In general, a digital synchronous circuit includes a network of combinational clouds interconnected by sequential state elements. Clock skewing is a widely used optimization technique in conventional application-specific integrated circuit (ASIC) designs. Traditionally, clock skewing works by delaying the clock signal using combinational buffers within the clocking network. Conventional design of the clocking networks is based on the assumption that every register receives the clock signal (assuming single phase clocking) at exactly the same time. In practice, guaranteeing simultaneity of clock arrival times is not possible due to gate and interconnect delays. The difference in the clock arrival times at two sequential state elements is referred to as the clock skew between those sequential state elements. There is an extensive body of literature, spanning two decades, on optimizing the design of clock networks aimed at minimizing the skew in order to maximize a clock frequency. Unfortunately, clock buffers consume large amounts of area within an integrated circuit (IC) and also can consume large amounts of power.
Accordingly, techniques and methods are needed to provide clock skew in digital synchronous circuits so that less area and power are consumed within an IC.